\doxysection{LPTIM\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_l_p_t_i_m___type_def}{}\label{struct_l_p_t_i_m___type_def}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}}


LPTIMIMER.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a5b270971af377ca8387e65bb9267dd0e}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a09774178fdd5412dd8f4539f431b15c9}{ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a58d1ea360d85b8d4f13e4f6bba594ea7}{IER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a35c555cdc39e12f291f1e96bdf953ec4}{CFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_aa4900090e51a693ed07d4a90eb45ddf8}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a0f22edd659052ecb52c692e507a8ebdc}{CMP}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a0aa430eedacf1806e078057cd5e6970c}{ARR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a8c510cd4e483030373cb03eb347d65df}{CNT}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a73262af853eb1a01aea32967fa19e3a7}{RESERVED1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_l_p_t_i_m___type_def_a71583a9ce4c19ca3b4f7f1e7f7b7b662}{CFGR2}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
LPTIMIMER. 

\label{doc-variable-members}
\Hypertarget{struct_l_p_t_i_m___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_l_p_t_i_m___type_def_a0aa430eedacf1806e078057cd5e6970c}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!ARR@{ARR}}
\index{ARR@{ARR}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ARR}{ARR}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a0aa430eedacf1806e078057cd5e6970c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+ARR}

LPTIM Autoreload register, Address offset\+: 0x18 \Hypertarget{struct_l_p_t_i_m___type_def_a35c555cdc39e12f291f1e96bdf953ec4}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!CFGR@{CFGR}}
\index{CFGR@{CFGR}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFGR}{CFGR}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a35c555cdc39e12f291f1e96bdf953ec4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+CFGR}

LPTIM Configuration register, Address offset\+: 0x0C \Hypertarget{struct_l_p_t_i_m___type_def_a71583a9ce4c19ca3b4f7f1e7f7b7b662}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!CFGR2@{CFGR2}}
\index{CFGR2@{CFGR2}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFGR2}{CFGR2}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a71583a9ce4c19ca3b4f7f1e7f7b7b662} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+CFGR2}

LPTIM Configuration register, Address offset\+: 0x24 \Hypertarget{struct_l_p_t_i_m___type_def_a0f22edd659052ecb52c692e507a8ebdc}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!CMP@{CMP}}
\index{CMP@{CMP}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CMP}{CMP}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a0f22edd659052ecb52c692e507a8ebdc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+CMP}

LPTIM Compare register, Address offset\+: 0x14 \Hypertarget{struct_l_p_t_i_m___type_def_a8c510cd4e483030373cb03eb347d65df}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!CNT@{CNT}}
\index{CNT@{CNT}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CNT}{CNT}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a8c510cd4e483030373cb03eb347d65df} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+CNT}

LPTIM Counter register, Address offset\+: 0x1C \Hypertarget{struct_l_p_t_i_m___type_def_aa4900090e51a693ed07d4a90eb45ddf8}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!CR@{CR}}
\index{CR@{CR}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_aa4900090e51a693ed07d4a90eb45ddf8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+CR}

LPTIM Control register, Address offset\+: 0x10 \Hypertarget{struct_l_p_t_i_m___type_def_a09774178fdd5412dd8f4539f431b15c9}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a09774178fdd5412dd8f4539f431b15c9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+ICR}

LPTIM Interrupt Clear register, Address offset\+: 0x04 \Hypertarget{struct_l_p_t_i_m___type_def_a58d1ea360d85b8d4f13e4f6bba594ea7}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!IER@{IER}}
\index{IER@{IER}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IER}{IER}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a58d1ea360d85b8d4f13e4f6bba594ea7} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+IER}

LPTIM Interrupt Enable register, Address offset\+: 0x08 \Hypertarget{struct_l_p_t_i_m___type_def_a5b270971af377ca8387e65bb9267dd0e}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a5b270971af377ca8387e65bb9267dd0e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+ISR}

LPTIM Interrupt and Status register, Address offset\+: 0x00 \Hypertarget{struct_l_p_t_i_m___type_def_a73262af853eb1a01aea32967fa19e3a7}\index{LPTIM\_TypeDef@{LPTIM\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!LPTIM\_TypeDef@{LPTIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_l_p_t_i_m___type_def_a73262af853eb1a01aea32967fa19e3a7} 
uint32\+\_\+t LPTIM\+\_\+\+Type\+Def\+::\+RESERVED1}

Reserved, 0x20 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
